Semiconductor Physics, Quantum Electronics & Optoelectronics, 25 (1), P. 036-042 (2022).
DOI: https://doi.org/10.15407/spqeo25.01.036

Special regularities for lowering temperature during growth of high-quality CdTe semiconductor layers
P.P. Moskvin1, L.V. Rashkovetskyi2, S.V. Plyatsko2, S.P. Semenets1

1Zhytomyr Polytechnic State University
103, Chudnivska str., 10005 Zhytomyr, Ukraine
E-mail: moskvinpavel56@gmail.com
1V. Lashkaryov Institute of Semiconductor Physics, NAS of Ukraine
41, prospect Nauky, 03680 Kyiv, Ukraine
E-mail: rashlv@ukr.net

Abstract. To obtain epitaxial layers of A2B6 semiconductors with increased structural perfection from their own liquid phase, it has been proposed to use a technological process in which the synthesis temperature varies in such a manner that ensures a constant growth rate of layers during the whole process. The regularities of temperature variation with time for this process have been found on the basis of diffusion crystallization model. The developed model is realized by numerical methods and applied to description of the growth of cadmium telluride layers. Quantitative data on variations of synthesis temperature have been obtained, which can serve as a basis for choosing the temperature-time regimes of growth of cadmium telluride layers with a constant and required rate of solid phase formation.

Keywords:A2B6 solid solution, epitaxial film, CdTe compound, liquid phase epitaxy, kinetics of crystallization, supercooling technology.

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