Semiconductor Physics, Quantum Electronics & Optoelectronics. 2012. V. 15, N 1. P. 077-079.
References 1. S. Thompson, et al. A 90 nm logic technology featuring 50nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 um2 SRAM Cell. International Electron Devices Meeting Technical Digest, pp. 61-64, 2002.https://doi.org/10.1109/IEDM.2002.1175779 2. T. Ghani, et al. A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. International Electron Devices Meeting Technical Digest, pp. 978-980, 2003. 3. P.I. Baranskii, I.V. Dakhovskii, V.V. Kolomoets, et al. Intervalley scattering in n-Si in the temperature range 78-300 K. Fiz. Tekh. Polupov. 10(8), pp. 480-1482 (1976). |