Semiconductor Physics, Quantum Electronics and Optoelectronics, 11 (3) P. 203-208 (2008).
DOI: https://doi.org/10.15407/spqeo11.03.203


References

1. E. Simoen and C. Claeys, On the flicker noise in submicron silicon MOSFETs // Solid-State Electronics 43(5), p. 865-882 (1999).
https://doi.org/10.1016/S0038-1101(98)00322-0
2. N. Lukyanchikova, N. Garbar, V. Kudina, A. Smolanka, M. Lokshin, E. Simoen and C. Claeys, High gate voltage drain current leveling off and its low-frequency noise in 65 nm fully-depleted strained and non-strained SOI nMOSFETs // SolidState Electronics 52(5), p. 801-807 (2008).
https://doi.org/10.1016/j.sse.2007.12.011
3. R. Jayaraman and C. Sodini, A 1/f technique to extract the oxide trap density near the conduction band edge of silicon // IEEE Trans. Electron Devices 36(9), p. 1773-1782 (1989).
https://doi.org/10.1109/16.34242
4. N. Lukyanchikova, N. Garbar, V. Kudina, A. Smolanka, E. Simoen and C. Claeys, Behavior of the 1/f noise and electron mobility in 65 nm FD SOI nMOSFETs employing different tensile-straininducing techniques, In: 19th International Conference on Noise and Fluctuations - ICNF 2007, Eds. M. Takano, Y. Yamamoto, M. Nakao, p. 39-42, American Institute of Physics (2007).
https://doi.org/10.1063/1.2759632
5. J. Ramos, E. Augendre, A. Kottantharayil, A. Mercha, E. Simoen, M. Rosmeulen, S. Severi, C. Kerner, T. Chiarella, A. Nackaerts, I. Ferain, T. Hoffmann, M. Jurczak and S. Biesemans, Expderimental evidence of short-channel electron mobility degradation caused by interface charges located at the gate-edge of Triple-Gate FinFETs, In: Proc 8th ICSICT, p. 72-74, Shanghai, China (2006).
https://doi.org/10.1109/ICSICT.2006.306080
6. V. Iyengar, A. Kottantharayil, F. Tranjan, M. Jurczak and K. De Meyer, Extraction of the top and sidewall mobility in FinFETs and the impact of Fin-patterning processes and gate dielectrics on mobility // IEEE Trans. Electron Devices 54(5), p. 1177-1184 (2007).
https://doi.org/10.1109/TED.2007.894937
7. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tebery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R.Lin and D. Kyser, FinFET scalling to 10 nm gate length, In: IEDM Tech. Dig., p. 251-254 (2002).
8. N. Lukyanchikova, M. Petrichuk, N. Garbar, A. Mercha, E. Simoen and C. Claeys, Electron valence-band tunneling-induced Lorentzian noise in deep submicron silicon-on-insulator metaloxide-semiconductor field-effect transistors // J. Appl. Phys. 94, p. 4461-4469 (2003).
https://doi.org/10.1063/1.1604452
9. N. Lukyanchikova, Noise research of nanoscaled SOI devices, In: Nanoscaled Semiconductor-onInsulator Structures and Devices, Eds. S. Hall, A. Nazarov and V. Lysenko. Springer, 2007, p. 181- 198.
https://doi.org/10.1007/978-1-4020-6380-0_14