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Semiconductor Physics, Quantum Electronics & Optoelectronics. 2006. V. 9, N 2. P. 040-044.
Fabrication and characterization of a 0.14 μm CMOS device
using ATHENA and ATLAS simulators
1Dept. of Electrical, Electronic and Systems Engineering, Faculty of Engineering
43600 University Kebangsaan Malaysia, MALAYSIA
Phone: 6-03-89296309; fax: 6-03-89296146
E-mail: ibrahim@vlsi.eng.ukm.my; burhan@eng.ukm.my
Abstract. A 0.14 µm CMOS transistor with two levels of interconnection was designed
and simulated to investigate its functionality and characteristics. ATHENA and ATLAS
simulators were used to simulate the fabrication process and to validate the electrical
characteristics, respectively. A scaling factor of 0.93 was applied to a 0.13 µm CMOS.
The parameters being scaled are the effective channel length, the density of ion
implantation for threshold voltage (V th ) adjustment, and the gate oxide thickness. In order
to minimize high field effects, the following additional techniques were implemented:
shallow trench isolation, sidewall spacer deposition, silicide formation, lightly doped
drain implantation, and retrograde well implantation. The results show that drain current
(I D ) increases as the levels of interconnection increases. The important parameters for
NMOS and PMOS were measured. For NMOS, the gate length (L g ) is 0.133 µm, V th is
0.343138 V, and the gate oxide thickness (T ox ) is 3.46138 nm. For PMOS, L g is 0.133
µm, V th is −0.378108 V, and T ox is 3.46167 nm. These parameters were validated and the
device was proven to be operational.
Keywords: gate length, threshold voltage, gate oxide thickness.
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