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Semiconductor Physics, Quantum Electronics & Optoelectronics. 2011. V. 14, N 2. P. 203-208.
Impact of sidewall spacer on gate leakage behavior
of nano-scale MOSFETs
1Department of Electronics and Communication, National Institute of Technology, Hamirpur
Hamirpur (H.P)-177005, India
E-mail: ashwani_paper@yahoo.com; kapoor@nitham.ac.in
Abstract.
Semiconductor devices with a low gate leakage current are preferred for low
power application. As the devices are scaled down, sidewall spacer for CMOS transistor
in nano-domain becomes increasingly critical and plays an important role in device
performance evaluation. In this work, gate tunneling currents have been modeled for a
nano-scale MOSFET having different high-k dielectric spacer such as SiO 2 , Si 3 N 4 ,
Al 2 O 3 , HfO 2 . The proposed model is compared and contrasted with Santaurus simulation
results and reported experimental result to verify the accuracy of the model. The
agreement found was good, thus validating the developed analytical model. It is observed
in the results that gate leakage current decreases with the increase of dielectric constant
of the device spacer. Further, it is also reported that the spacer materials impact the
threshold voltage, on current, off current, drain induced barrier lowering and sub-
threshold slope of the device.
Keywords: MOSFET, spacer, leakage current.
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